Evans, in U.S. Pat. No. 5,996,097, granted Nov. 30, 1999, teaches a technique for efficiently testing a memory or an array of logic configured as an addressed array by simultaneously selecting all the addresses, simultaneously writing patterns into the selected memory or logic, and simultaneously reading and comparing each of the multiple results with the desired outcomes. Evans correctly points out that this technique can significantly reduce the test time required to test such a structure, which in turn would significantly reduce the cost of the product since the cost of testing a complex semiconductor product is a significant portion of the cost of producing such products. Still, selecting all of the address lines in a traditional memory is not desirable since different states must be stored into adjacent bits of the memory in order to test for shorts between the bits. Furthermore, Evans' approach requires comparison logic at each of the selected addresses to compare the results with the desired outcomes, which while readily available in a content addressable memory that Evans used as an example, it is not readily available in a standard memory.
This inventor has disclosed a serial decoding technique in US Published Application Number 2007/0050596, published on Mar. 1, 2007, that successively halves the number of selected word lines as each address bit is acquired until, on acquiring the last address bit, a single word line is selected. Because the structure is a circular shift register, at any point in this serial address generation cycle, the structure can alternatively rotate the selection bits in its shift register to select a new set of address lines. In that application the inventor also disclosed a way to improve the access of a memory with serial output when the last two possible values from the selected memory outputs contain the same data.
The serial shift register decoder as shown in FIG. 1 is comprised of a single bit address input; a multiplicity of shift register stages, each with a word line output, where each of the shift register stages is connected to a previous and a next shift register stage such that the data shifts through the shift register stages in a circular fashion, the input of half of the shift register stages is the AND of the said address input and the previous shift register stage, and the input of the other half of the shift register stages is the AND of the inverse of the address input and the previous shift register stage. The word lines in FIG. 1 each correspond to a unique address between 0 and 15 and are sorted, by wiring, into sequential order. Table 1 below shows the relationship between the bit locations and their addresses for 2, 3 and 4 bit decodes.
TABLE 1Shift Bit #0123456789101112131415Polarity−++++−++−−+−+−−−4 bitAddress0137151413116129251048DecodePolarity−+++−+−−3 bitAddress0137 6 5 2 4DecodePolarity−++−2 bitAddress0132Decode
Still, while the advantages of serially addressing a memory in today's high speed communications technology was discussed in the disclosure of the aforementioned application, the advantages of testing memories with such a decode structure was not discussed. Furthermore, while a technique was previously presented to improve the latency of the memory by one clock cycle when selecting between outputs, this disclosure extends the capability with new techniques.